Work package 1: architecture
The analysis of predictability vs. efficiency trade-offs is grounded on formal and accurate modelling and understanding of the characteristics of the computing fabric, namely hardware architectures. Architectural modelling will be based on an existing virtual platform, representative of complex state-of-the-art hardware architectures. The platform provides functional simulation models for processor cores (with advanced architectural features), memory blocks (caches, buffers, etc.), input-output peripherals, and system interconnect (system bus, onchip network). Functional component models are augmented with views of non-functional static (e.g. cost) and dynamic (e.g. power) properties for all components. Thus, it is possible to analyse average-case performance and power (energy) during accurate full-system functional simulation.
The objective of the work package is to integrate the functional simulation model of the virtual platform with formal analysis models and methods that are better suited for the assessment of worst-case properties. Both simulation and analysis models should be based on formal specifications of an architecture to allow for proofs of correctness. Sensitivity analyses for sets of architectural parameters will be performed, one determining the dependency of efficiency on these parameters and the other determining the influence of the same parameters on predictability. The goal is to identify parameter settings that offer a good combination of efficiency and predictability.
Main tasks
- Automotive target platform & requirements
- Architectural extensions for supporting predictability in single-processor and multi-processor environments
- Firmware and low-level middleware support libraries for memory management and communication
- Sensitivity analyses for architectural parameters
- Adaptation and extension of aiT and StackAnalyzer