Saarland University
Saarbrücken, Germany
www.uni-saarland.de
Role
Project coordinator, leading WP5, timing analysis, static program analysis, compilation, system design.
Specific skills
The Compiler Design Lab at the Saarland University together with its spin-off company AbsInt is leading worldwide in the area of timing analysis of hard real-time systems. The development of aiT, AbsInt’s award-winning timing-analysis tool, is based on decades of research on static program analysis at Reinhard Wilhelm’s Chair for Programming Languages and Compiler Construction.
Static analysis of an embedded program is used to derive invariants about execution states for all inputs to the program. These invariants allow the derivation of reliable upper and lower bounds on the execution times of programs on a given hardware architecture. This technology has been developed in a series of national and EU-funded projects. The most important of those was the IST project DAEDALUS, led by Airbus. DAEDALUS was concerned with the derivation of guarantees for safety-critical avionics software and was considered a highly successful project. The aiT technology developed in the project has been instantiated for numerous processors ranging from simple microprocessors up to most complex processors of the PowerPC family. The tool is widely used in the European aeronautics and automotive industry. By working on this wide range of architectures, Reinhard Wilhelm’s group and AbsInt have gained deep insights into the predictability properties of hardware architectures.
While the application of static analysis to the determination of bounds on execution times is probably the most spectacular application pursued at Saarland University, considerable foundational work has been done as well. For example, a new approach to static analysis based on 3-valued logic has been developed together with the Tel Aviv University and University of Wisconsin at Madison. It has been successfully applied to systems with dynamically growing and shrinking sets of objects/threads/actors. This technology is extended to systems with dynamically changing communication topologies in the nationally funded project AVACS (Automatic Verification and Analysis of Complex Systems). Reinhard Wilhelm also directs the timing analysis activity in the European Network of Excellence ARTIST2 that combines all European groups working in the area of embedded systems design.
Key personnel
- Reinhard Wilhelm — compiler technology, WCET expertise
- Oleg Parshin — timing analysis, integration with code synthesis
- Sebastian Altmeyer — cache analysis, determination and reduction of context-switch costs
- Gernot Gebhard — compiler design, timing analysis, determination and reduction of context-switch costs
- Daniel Grund — cache predictability and compilation
- Jan Reineke — static program analysis, timing anomalies, cache predictability
PREDATOR-related publications
- Parametric Timing Analysis for Complex Architectures
By Sebastian Altmeyer, Björn Lisper, and Reinhard Wilhelm, Saarland University, and Christian Hümbert, AbsInt.
In: Proceedings of the 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) 2008. - CAMA: Cache-Aware Memory Allocation for WCET Analysis
By Jörg Herter, Jan Reineke, and Reinhard Wilhelm, Saarland University.
In: Proceedings Work-In-Progress Session of the 20th Euromicro Conference on Real-Time Systems. - WCET Analysis for Preemptive Systems
By Sebastian Altmeyer and Gernot Gebhard, Saarland University.
In: Proceedings of the 8th International Workshop on Worst-Case Execution Time (WCET) Analysis. - Estimating the Performance of Cache Replacement Policies
By Daniel Grund and Jan Reineke, Saarland University.
In: MEMOCODE 2008: Proceedings of the 6th IEEE/ACM International Conference on Formal Methods and Models for Code Design. - Relative Competitiveness of Cache Replacement Policies
By Jan Reineke and Daniel Grund, Saarland University.
In: SIGMETRICS 2008: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems. - Relative Competitive Analysis of Cache Replacement Policies
By Jan Reineke and Daniel Grund, Saarland University.
In: LCTES 2008: Proceedings of the 2008 ACM SIGPLAN–SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. - Abstract Interpretation with Applications to Timing Validation (PDF, 180kB)
By Reinhard Wilhelm and Björn Wachter, Saarland University.
In: CAV 2008: Proceedings of the 20th International Conference on Computer Aided Verification. - A New Notion of Useful Cache Block to Improve the Bounds of Cache-Related Preemption Delay
By Sebastian Altmeyer and others, Saarland University.
In: Proceedings of ECRTS 2009. - Abstract Interpretation of FIFO Replacement
By Daniel Grund and others, Saarland University.
In: Proceedings of SAS 2009. - Branch Target Buffers: WCET Analysis and Timing Predictability
By Daniel Grund and others, Saarland University.
In: Proceedings of RTCSA 2009. - Cache-Related Preemption Delay Computations for Set-Associative Caches — Pitfalls and Solutions
By Claire Burguière, Jan Reineke, and Sebastian Altmeyer, Saarland University.
In: Proceedings of WCET 2009. - Sound and Efficient WCET Analysis in the Presence of Timing Anomalies
By Jan Reineke and others, Saarland University.
In: Proceedings of WCET 2009. - Computing the Maximum Blocking Time for Scheduling with Deferred Preemption
By Sebastian Altmeyer and others, Saarland University.
In: Proceedings of STFSSD 2009. - Improving Timing Analysis for MATLAB Simulink/Stateflow
By Lili Tan and others, Saarland University.
In: Proceedings of ACES-MB 2009. - Making Dynamic Memory Allocation Static to Support WCET Analyses
By Jörg Herter and Jan Reineke, Saarland University.
In: Proceedings of WCET 2009. - Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
By Reinhard Wilhelm et al., Saarland University.
In: IEEE TCAD, 28 (7), 2009. - Operating Mode Specific WCET Analysis
By Philipp Lucas and others, Saarland University.
In: Proceedings of JRWRTC 2009. - Precomputing Memory Locations for Parametric Allocations
By Jörg Herter and others, Saarland University.
In: Proceedings of WCET’10. - Static Timing Analysis for Hard Real-Time Systems
By Reinhard Wilhelm and others, Saarland University.
In: Proceedings of VMCAI’10. - Towards Precise PLRU Cache Analysis (PDF, 325kB)
By Daniel Grund, Saarland University, and Jan Reineke, University of California, Berkeley.
In: Proceedings of WCET’10.